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  Home > Pure-play Wafer Foundry > Foundry Services > Foundry Support > Process Design Kit
 
Process Design Kit
   
 

Device Models

  • Nonlinear devices
  • Passive devices
  • S-parameter
  • Statistical Variation
  • Thermal (for some PDKs)

Schematic Symbols and Libraries

  • Parameterized schematic symbols
  • Technology specific component libraries
  • Simulation include blocks

Layout Libraries and Pcells

  • Parameterized Cells (Pcells)
  • Standard layout cells
  • Layer definitions

Technology & Process Files

  • Substrate files
  • Layer maps
  • Process options

Verification Decks

  • DRC (Design Rule Check)
  • LVS (Layout vs Schematic)

 

KEYSIGHT CADENCE

EM simulation support